An MOS transistor that includes a trench gate structure offers important advantages over a planar transistor for high current, low voltage switching applications. In the latter configuration, constriction occurs at high current flows, an effect that places substantial constraints on the design of a transistor intended for operation under such conditions.
A trench gate of a DMOS device typically includes a trench extending from the source to the drain and having sidewalls and a floor that are each lined with a layer of thermally grown silicon dioxide. The lined trench is filled with doped polysilicon. The structure of the trench gate allows less constricted current flow and, consequently, provides lower values of specific on-resistance. Furthermore, the trench gate makes possible a decreased cell pitch in an MOS channel extending along the vertical sidewalls of the trench from the bottom of the source across the body of the transistor to the drain below. Channel density is thereby increased, which reduces the contribution of the channel to on-resistance. The structure and performance of trench DMOS transistors are discussed in Bulucea and Rossen, “Trench DMOS Transistor Technology for High-Current (100 A Range) Switching,” in Solid-State Electronics, 1991, Vol. 34, No. 5, pp 493-507, the disclosure of which is incorporated herein by reference. In addition to their utility in DMOS devices, trench gates are also advantageously employed in insulated gate bipolar transistors (IGBTs), MOS-controlled thyristors (MCTs), and other MOS-gated devices.
FIG. 1 schematically depicts the cross-section of a trench MOS gate device 100 of the prior art. Although FIG. 1 shows only one MOSFET, a typical device currently employed in the industry consists of an array of MOSFETs arranged in various cellular or stripe layouts.
Device 100 includes a doped (depicted as N+) substrate 101 on which is grown a doped epitaxial layer 102. Epitaxial layer 102 includes drain region 103, heavily doped (P+) body regions 104, and P-wells 105. Abutting body regions in epitaxial layer 103 are heavily doped (N+) source regions 106, which are separated from each other by a gate trench 107 that has dielectric sidewalls 108 and floor 109. Gate trench 107 is substantially filled with gate semiconductor material 110. Because the source regions 106 and gate semiconductor material 110 have to be electrically isolated for device 100 to function, they are covered by a dielectric layer 111. Contact openings 112 enable metal 113 to contact body regions 104 and source regions 106.
Contact openings 112 are formed in dielectric layer 111, which typically is a deposited layer of oxide, by conventional mask/etch techniques. The size of device 100 depends on the minimum thickness of dielectric needed for isolation (the lateral distance between a source region 106 and gate trench 107) and on the tolerance capabilities of the mask/etch procedures. The thickness of dielectric layer 111 is determined not only by the minimum required voltage isolation but also on the need to minimize source-to-gate capacitance, which affects device switching speed and switching losses. Switching losses are directly proportional to the capacitance, which is in turn inversely proportional to the dielectric thickness. Therefore there is a typical minimum thickness of about 0.5-0.8 μm for dielectric layer 111 in prior art device 100.
As just noted, the required minimum thickness of dielectric layer 111 imposes limitations on the minimum size of device 100. It would be desirable to be able to reduce the size and improve the efficiency of semiconductor devices. The present invention provides these benefits.